This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-266085, filed Sep. 20, 1999, the entire contents of which are incorporated herein by reference.
This invention relates to a nonvolatile semiconductor memory device capable of storing, for example, multivalued data.
A NAND flash memory using an EEPROM has been proposed as an electrically rewritable nonvolatile semiconductor memory. In the NAND flash memory, the sources and drains of memory cells arranged side by side are connected in series and the series connection of the memory cells is connected as one unit to a bit line. In the NAND flash memory, all or half of the cells arranged in the direction of row are written into or read from all at once. Recently, a multivalued memory that enables data items to be stored in one cell in a NAND flash memory has been developed.
FIG. 3 shows the relationship between the data in a memory cell in an ordinary multivalued memory and the threshold voltage of the memory cell. The data items in a memory cell, or state xe2x80x9c0xe2x80x9d to state xe2x80x9c3xe2x80x9d, are defined in ascending order, starting from the lowest threshold voltage of the memory cell. When erasing is done, the data in the memory cell goes to state xe2x80x9c0xe2x80x9d. A write operation causes the threshold voltage of the cell to move to a higher level. When 2-bit data is stored in a single cell, the 2-bit data is separated into first-page data and second-page data. The first-page data and second-page data are switched using an address.
FIG. 4 shows a general method of writing data into a multivalued memory. When data is written into a memory cell, the first-page data is written. Then, the second-page data is written. When the write data constituting the first-page or second-page data is xe2x80x9c1xe2x80x9d, the threshold voltage of the memory cell does not change in the write operation, with the result that the data in the memory cell remains unchanged. Namely, the data is not written. When write data constituting the first-page or second-page data is xe2x80x9c0xe2x80x9d, the threshold voltage of the memory cell is changed in the write operation. As a result, the data in the memory cell is changed, causing the data to be written.
It is assumed that the data in the memory cell in the erased state is in state xe2x80x9c0xe2x80x9d. First, the first-page data is written into the memory cell. When the write data is xe2x80x9c1xe2x80x9d, the data in the memory cell remains in state xe2x80x9c0xe2x80x9d. When the write data is xe2x80x9c0xe2x80x9d, the data in the memory cell goes to state xe2x80x9c1xe2x80x9d.
Next, the second-page data is written. At this time, when write data xe2x80x9c0xe2x80x9d is externally supplied to the memory cell whose data has become state xe2x80x9c1xe2x80x9d as a result of the first-page write operation, the data in the memory cell is brought into state xe2x80x9c3xe2x80x9d. Moreover, when data xe2x80x9c0xe2x80x9d is externally supplied to the memory cell whose data has remained in state xe2x80x9c0xe2x80x9d as a result of the first-page write operation, the data in the memory cell is brought into state xe2x80x9c2xe2x80x9d.
Furthermore, when data xe2x80x9c1xe2x80x9d is externally supplied to the memory cell whose data has become state xe2x80x9c1xe2x80x9d as a result of the first-page write operation, the data in the memory cell is allowed to remain in state xe2x80x9c1xe2x80x9d. In addition, when data xe2x80x9c1xe2x80x9d is externally supplied to the memory cell whose data has remained in state xe2x80x9c0xe2x80x9d as a result of the first-page write operation, the data in the memory cell is allowed to remain in state xe2x80x9c0xe2x80x9d.
On the other hand, when the data stored in the memory cell is read, the second-page data is read first and the first-page data is read. With the definition of FIG. 3, when the second-page data is read, if the data in the memory cell is in state xe2x80x9c0xe2x80x9d or state xe2x80x9c1xe2x80x9d, the read-out data will be xe2x80x9c1xe2x80x9d. Furthermore, if the data in the memory cell is in state xe2x80x9c2xe2x80x9d or state xe2x80x9c3xe2x80x9d, the read-out data will be xe2x80x9c0xe2x80x9d. For this reason, when the second-page data is read, a judgment can be made through only one operation of judging whether the data in the memory cell is in either state xe2x80x9c1xe2x80x9d or below or state xe2x80x9c2xe2x80x9d or above.
In contrast, when the first page data is read, if the data in the memory cell is in state xe2x80x9c0xe2x80x9d or state xe2x80x9c2xe2x80x9d, the data to be read will be xe2x80x9c1xe2x80x9d. If the data in the memory cell is in state xe2x80x9c1xe2x80x9d or state xe2x80x9c3xe2x80x9d, the data to be read will be xe2x80x9c0xe2x80x9d. Consequently, the first page requires a total of three read operations for the following judgments: a judgment whether the data in the memory cell is in either state xe2x80x9c0xe2x80x9d or state xe2x80x9c1xe2x80x9d or above, a judgment whether the data in the memory cell is in either state xe2x80x9c1xe2x80x9d or below or state xe2x80x9c2xe2x80x9d or above, and a judgment whether the data in the memory cell is in either state xe2x80x9c2xe2x80x9d or below or state xe2x80x9c3xe2x80x9d.
Therefore, an ordinary nonvolatile semiconductor memory device requires many operations in reading the data from the memory cells, taking a long time to read the data.
It is, accordingly, an object of the present invention to overcome the above disadvantage by providing a nonvolatile semiconductor memory device capable of reducing the number of operations in reading data and shortening the data read time.
The foregoing object is accomplished by providing a nonvolatile semiconductor memory device comprising: a memory element which is connected to a bit line and a word line and stores one of state xe2x80x9c0xe2x80x9d, state xe2x80x9c1xe2x80x9d, state xe2x80x9c2xe2x80x9d, and state xe2x80x9c3xe2x80x9d of data that differ in threshold voltage; a data storage circuit which is connected to the bit line and stores not only data of a first or a second logical level externally supplied but also the data of the first or second level read from the memory element; and a control circuit which controls not only the potential on the bit line and that on the word line but also the operation of the data storage circuit, wherein the control circuit operates in such a manner that in a first operation, the control circuit changes the data in the memory element from the state xe2x80x9c0xe2x80x9d to state xe2x80x9c1xe2x80x9d when the data in the data storage circuit is data of the first logical level and keeps the data in the memory element in the state xe2x80x9c0xe2x80x9d when the data in the data storage circuit is data of the second logical level, that in a first verify operation of verifying whether the data has reached state xe2x80x9c1xe2x80x9d, the control circuit brings the data in the data storage circuit to the second logical level when the data in the data storage circuit is at the first logical level and the data has reached state xe2x80x9c1xe2x80x9d, keeps the data in the data storage circuit at the first logical level when the data has not reached state xe2x80x9c1xe2x80x9d, keeps the data in the data storage circuit at the second logical level when the data in the data storage circuit is at the second logical level, and carries out the first operation until the data in the data storage circuit has reached the second logical level, and that in a second operation, the control circuit changes the data in the memory element from state xe2x80x9c1xe2x80x9d to state xe2x80x9c2xe2x80x9d when the data in the data storage circuit is data of the first logical level externally supplied and the data in the memory element is in state xe2x80x9c1xe2x80x9d, and changes the data in the memory element from state xe2x80x9c0xe2x80x9d to state xe2x80x9c3xe2x80x9d when the data in the memory element is in state xe2x80x9c0xe2x80x9d.
The foregoing object is further accomplished by providing a nonvolatile semiconductor memory device comprising: a memory element which is connected to a bit line and a word line and stores one of state xe2x80x9c0xe2x80x9d, state xe2x80x9c1xe2x80x9d, state xe2x80x9c2xe2x80x9d, and state xe2x80x9c3xe2x80x9d of data that differ in threshold voltage; a first storage circuit which is connected to the bit line and stores data of a first or a second logical level externally supplied; a second storage circuit which is connected to the bit line and stores the data of the first or second level read from the memory element; and a control circuit which controls not only the potential on the bit line and that on the word line but also the operation of the first and second storage circuits, wherein the control circuit operates in such a manner that in a first operation, the control circuit changes the data in the memory element from state xe2x80x9c0xe2x80x9d to state xe2x80x9c1xe2x80x9d when the data in the first data storage circuit is data of the first logical level and keeps the data in the memory element at the state xe2x80x9c0xe2x80x9d when the data in the first storage circuit is data of the second logical level, that in a first verify operation of verifying whether the data has reached state xe2x80x9c1xe2x80x9d, the control circuit brings the data in the first storage circuit to the second logical level when the data in the first storage circuit is at the first logical level and the data has reached state xe2x80x9c1xe2x80x9d, keeps the data in the first storage circuit at the first logical level when the data has not reached state xe2x80x9c1xe2x80x9d, keeps the data in the first storage circuit at the second logical level when the data in the first storage circuit is at the second logical level, and carries out the first operation until the data in the first storage circuit has reached the second logical level, that in a second operation, the control circuit stores the data read from the memory element into the second storage circuit, changes the data in the memory element from state xe2x80x9c1xe2x80x9d to state xe2x80x9c2xe2x80x9d when the data in the first storage circuit is data of the first logical level externally supplied, changes the data in the memory element from state xe2x80x9c0xe2x80x9d to state xe2x80x9c3xe2x80x9d when the data in the memory element is in state xe2x80x9c0xe2x80x9d, and keeps the data in the memory element when the data in the memory element is data of the second logical level, that in a second verify operation of verifying whether the data in the memory element has reached state xe2x80x9c2xe2x80x9d, the control circuit brings the data in the first storage circuit to the second logical level when the data has reached state xe2x80x9c2xe2x80x9d in a case where the data in the first storage circuit is at the first logical level and the data in the memory element is in state xe2x80x9c1xe2x80x9d before the second operation is carried out, keeps the data in the first storage circuit at the first logical level when the data has not reached state xe2x80x9c2xe2x80x9d, and brings the potential on the bit line to which the memory element is connected to the first logical level and the data in the first storage circuit to the first logical level when the data in the second storage circuit is at the second logical level in a case where the data in the memory element is in state xe2x80x9c0xe2x80x9d before the second operation is carried out, and that in a third verify operation of verifying the data has reached state xe2x80x9c3xe2x80x9d, the control circuit brings the data in the first storage circuit to the second logical level when the data in the first storage circuit is at the first logical level and the data has reached state xe2x80x9c3xe2x80x9d, keeps the data in the first storage circuit at the first logical level when the data has not reached state xe2x80x9c3xe2x80x9d, keeps the data in the first storage circuit at the second memory logical level when the data in the first storage circuit is at the second logical level, and carries out the second operation and second and third verify operations until the data in the first storage circuit has reached the second logical level.
The foregoing object is further accomplished by providing a nonvolatile semiconductor memory device comprising: a memory element which is connected to a bit line and a word line and stores one of an n number of data items made up of state xe2x80x9c0xe2x80x9d, state xe2x80x9c1xe2x80x9d, . . . state xe2x80x9cn xe2x80x9d (3xe2x89xa6n where n is a natural number); a data storage circuit which stores data of a first or a second memory logical level externally inputted; and a control circuit which controls not only the potential on the bit line and that on the word line but also the operation of the data storage circuit, wherein the control circuit, in a final write operation, brings state xe2x80x9c0xe2x80x9d of the smallest data stored in the memory element into state xe2x80x9cnxe2x80x9d of the largest data.
The foregoing object is further accomplished by providing a nonvolatile semiconductor memory device comprising: a memory element which is connected to a bit line and a word line and stores one of state xe2x80x9c0xe2x80x9d, state xe2x80x9c1xe2x80x9d, state xe2x80x9c2xe2x80x9d, and state xe2x80x9c3xe2x80x9d of data that differ in threshold voltage; a data storage circuit which is connected to the bit line and stores the data read from the memory element; and a control circuit which controls not only the potential on the bit line and that on the word line but also the operation of the data storage circuit, wherein the control circuit operates in such a manner that in a first read operation, the control circuit sets data of a first logical level in the data storage circuit when the data in the memory element is in either state xe2x80x9c0xe2x80x9d or state xe2x80x9c1xe2x80x9d, and sets data of a second logical level in the data storage circuit when the data in the memory element is in either state xe2x80x9c2xe2x80x9d or state xe2x80x9c3xe2x80x9d, and that in a second read operation, the control circuit sets data of the first logical level in the data storage circuit when the data in the memory element is in either state xe2x80x9c0xe2x80x9d or state xe2x80x9c3xe2x80x9d, and sets data of the second logical level in the data storage circuit when the data in the memory element is in either state xe2x80x9c1xe2x80x9d or state xe2x80x9c2xe2x80x9d.
With the present invention, the number of operations in reading the data can be reduced, which makes it possible to provide a nonvolatile semiconductor memory device capable of shortening the time required to read the data.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.